Sarkar22/hades-v-plus

Extended RISC-V soft core targeting the Basys3 FPGA: RV32IM + Zba + Zicsr/Zifencei/Zicntr on a 5-stage in-order pipeline with a branch predictor. Runs FreeRTOS with an interactive shell in Verilator simulation; formally verified multiply/divide unit. Built on TU Graz's HaDes-V.

语言：Assembly · GitHub 星标：3 · Fork：0

话题：artix-7 · basys3 · computer-architecture · cpu · formal-verification · fpga · freertos · hdl

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